Trimming is employed in the case of finely adjusting the characteristics of a semiconductor integrated circuit in whole, in particular, an analog circuit, by changing its resistance value, capacitance value, and inductance, aside from the inherent characteristics of a semiconductor device. Common methods of trimming include a laser trimming method, and a method of trimming by causing current to flow to pads connected to resistors and capacitors and by cutting wiring.
Herein, the laser trimming method is a method for executing trimming by directly burning off or cutting down resistance elements, and is capable of fine adjustment, but requires a dedicated apparatus using a laser. In contrast, the method of trimming by causing current to flow by use of the pads is a method for executing trimming by preparing beforehand a circuit wherein resistors and capacitors can be changed over, and by cutting wiring. This method is not capable of fine adjustment, but has an advantage of simplicity in that no dedicated apparatus is required.
More specifically, with the method of trimming by causing current to flow by use of the pads, a plurality of resistors, capacitors, and MOS gates, for use in adjustment, are connected to the pads of a trimming pattern, respectively, and when values of those elements need to be changed, an adjustment is made by causing current to flow between the pads, thereby cutting a thin line part interconnecting the pads.
A pattern shown in FIG. 1 is used as a layout pattern for conventional trimming. Pads A31, B32, connected to resistors and capacitors, respectively, and a thin line part 30 interconnecting the pads A31 and B32 are formed simultaneously with metallization during the step of forming multilayer wiring when manufacturing a semiconductor integrated circuit. The pads A31 and B32 are subsequently coated with an insulating film, but openings corresponding to the pads A31 and B32, respectively, are defined in the insulating film, thereby exposing the surface of metal. When a voltage is applied to the pads A31 and B32, current flows to the thin line part 30, whereupon the metal of the thin line part 30 undergoes fusion, and is cut upon completion of the fusion.
The mechanism of fusion cutting of metal is based on a phenomenon called the electromigration (EM), which is a phenomenon wherein flow of current causes atoms to migrate from one spot to the other spot. In this case, when electrons flow to unique grain boundaries (crevice between respective metal grains) occurring to a metal layer formed on a semiconductor by means of vapor deposition, sputtering, and so forth, atoms making up the metal layer collide with the electrons, thereby squeezing out metal. The phenomenon occurs due to the maximum current density of the metal layer such as metal patterns etc., and the smaller the cross-sectional area of the metal layer, orthogonal to the direction of current flow, becomes, the more prone to occurrence the phenomenon is.
A technical document relating the conventional technique described above is disclosed in JP, 2001-230325, A.
Incidentally, there has been continuing trends towards further miniaturization in the configuration of a semiconductor integrated circuit in recent years for higher performance of the semiconductor integrated circuit, and in addition, a level difference between the respective work surfaces of upper layers increases according as the upper layers become still higher due to further multilayer wiring. In the case of depositing metal over the level difference, the greater the level difference, the more insufficient coverage of the work surfaces with the metal becomes (the metal layers in stepped parts become thinner in thickness), so that the more miniaturized the metal pattern is, the higher there becomes the probability of a break occurring to the metal pattern, thus creating a cause for deterioration of reliability. Accordingly, a planarization process commonly called the CMP (Chemical Mechanical Polishing) process has since come to be used in order to improve the working accuracy of the metal pattern formed over the stepped parts. As a result of use of the CMP process, an interlayer insulating film formed underneath the metal layer is planarized, thereby improving the coverage with the metal.
Such planarization has become essential to the process of manufacturing a semiconductor integrated circuit, but has come to cause inconvenience to a pattern for trimming, formed on the interlayer insulating film.
With a conventional trimming pattern, thin line parts are formed on the stepped parts to facilitate cutting thereof, so that spots of the thin line parts, where a metal layer is thin in thickness, are cut off. However, as a result of improvement in the coverage with the metal, the metal in the thin line parts of the trimming pattern has come to be uniform in thickness, so that it has become difficult to easily cut the thin line parts by causing current to flow. Further, time required from the start of fusion of the metal until complete cutting has increased along with enhancement in tolerance, thereby lengthening work time required for trimming. Furthermore, there is no denying that continuous flow of high current between the pads of the trimming pattern will raise a possibility of an internal integrated circuit and internal elements as well being adversely affected.